★ WIDE MOAT STOCKS & COMPETITIVE ADVANTAGES ★
VOL. XCIV, NO. 247
Stock Profile
Taiwan Semiconductor Manufacturing Company Limited (2330) Moat Analysis
Taiwan Semiconductor Manufacturing Company Limited
2330 · Taiwan Stock Exchange
Weighted average of segment moat scores, combining moat strength, durability, confidence, market structure, pricing power, and market share.
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Overview
Taiwan Semiconductor Manufacturing Company is the dominant pure-play foundry for global chip designers and system companies. TrendForce reported a rounded 72% share of first-quarter 2026 top-ten foundry revenue, implying an approximate HHI of 5,287 on the disclosed shares. Q2 revenue reached NT$1.270T, gross margin 67.7%, and operating margin 60.3%; HPC was 66% of revenue, 7nm-and-below technologies were 77% of wafer revenue, and the new 2nm node contributed 3%. The verified moat mechanisms are frontier-scale capital and know-how, cumulative yield learning, process-specific design-in, and the OIP complement ecosystem. Temporary capacity scarcity is reflected in pricing and utilization but is not double-counted as a separate moat. Management raised 2026 capex to US$60B-US$64B and announced an additional US$100B Arizona investment, while warning that overseas fabs and the 2nm ramp dilute margins. Other risks include customer and North American concentration, cyclicality, Taiwan geopolitics, export controls, subsidized rivals, multi-foundry flows, and the unresolved Marlin ITC patent case. June was the latest monthly revenue release as of August 9; first-half revenue rose 35.6% to NT$2.404T. TWSE reported 25,932,370,067 common shares after the May cancellation; each NYSE ADS represents five common shares.
Primary segment
Semiconductor foundry services
Market structure
Quasi-Monopoly
Market share
72% (reported)
HHI: 5,287
Coverage
1 segments · 6 tags
Updated 2026-08-09
Segments
Semiconductor foundry services
Global outsourced semiconductor foundry services
Revenue
100%
Structure
Quasi-Monopoly
Pricing
strong
Share
72% (reported)
Peers
Moat Claims
Semiconductor foundry services
Global outsourced semiconductor foundry services
TSMC reports only one operating segment, the foundry segment. 2Q26 platform revenue was HPC 66%, smartphone 22%, IoT 5%, automotive 4%, digital consumer electronics 1%, and others 2%; 7nm-and-below technologies were 77% of wafer revenue.
Capex Knowhow Scale
Supply
Capex Knowhow Scale
Strength
Durability
Confidence
Evidence
TSMC combines massive capital deployment, owned fabs, engineering know-how and advanced-node scale that are hard for smaller foundries to replicate economically.
Capex Knowhow Scale moat: definition, examples, and stocks
Erosion risks
- Semiconductor downcycles can turn fixed-cost scale into negative operating leverage.
- Government subsidies can help Samsung, Intel, Rapidus and regional foundries build uneconomic capacity.
- Geopolitical risk around Taiwan could impair customer willingness to concentrate supply.
Leading indicators
- Advanced-node wafer capacity additions
- Capacity utilization by node
- Capex intensity versus Samsung and Intel Foundry
Counterarguments
- Scale does not immunize TSMC from cyclical overcapacity.
- Sovereign industrial policy can fund competitors even when private returns are unattractive.
Learning Curve Yield
Supply
Learning Curve Yield
Strength
Durability
Confidence
Evidence
A long history of high-volume process ramps compounds yield, defect-density, cycle-time and manufacturing-control know-how, especially at 7nm-and-below nodes.
Learning Curve Yield moat: definition, examples, and stocks
Erosion risks
- A major process inflection could reset accumulated yield advantages.
- Samsung or Intel Foundry could close the gap at a future node.
- Trade-secret leakage or talent loss could weaken process know-how advantages.
Leading indicators
- 2nm and 16-angstrom ramp milestones
- Advanced-node revenue share
- Yield and cycle-time customer commentary
Counterarguments
- Customers may push for second sources to avoid dependence on one leading-edge foundry.
- Technology leadership can narrow if rivals solve yield issues at a new transistor architecture.
Design In Qualification
Demand
Design In Qualification
Strength
Durability
Confidence
Evidence
Customer chips are designed around TSMC PDKs, IP libraries, mask sets, process rules and qualification flows, making late switching costly and risky.
Design In Qualification moat: definition, examples, and stocks
Erosion risks
- Open chiplet standards and multi-foundry design flows could reduce process lock-in.
- Large system customers can fund porting work when second sourcing becomes strategically important.
- Export controls can force redesigns away from TSMC processes for restricted customers.
Leading indicators
- Tape-outs on N2, A16 and A14-class nodes
- PDK and IP readiness milestones
- CyberShuttle participation
Counterarguments
- Well-funded customers can port designs if supply assurance outweighs time-to-market risk.
- EDA and IP vendors also support competing foundries.
Ecosystem Complements
Network
Ecosystem Complements
Strength
Durability
Confidence
Evidence
OIP, EDA partners, IP libraries, 3DFabric reference flows, broad process coverage and a large customer base create complements that make TSMC the default advanced foundry platform.
Ecosystem Complements moat: definition, examples, and stocks
Erosion risks
- EDA and IP vendors can make more flows multi-foundry.
- Open standards can reduce proprietary ecosystem dependence.
- Customer concentration may let the largest customers bypass parts of the ecosystem.
Leading indicators
- Number of OIP partners and certified IP blocks
- Process technologies deployed
- Products manufactured and customers served
Counterarguments
- Complementors are not exclusive to TSMC.
- A broader ecosystem can still be replicated for mature nodes or subsidized national foundry programs.
Evidence
raise our full-year 2026 capital budget to be between USD60 billion and USD64 billion
The current capital budget is a direct measure of the financial and execution scale required to keep expanding at the frontier.
annual capacity (in 12-inch equivalent wafers) exceeded 17 million wafers
Supports scale in installed manufacturing capacity.
faster yield improvement and shorter cycle time
TSMC identifies yield improvement and cycle time as core competitive dimensions.
2-nanometer technology entered volume production in 2025
Supports continued leading-edge ramp execution.
shipments of 2-nanometer accounted for 3% of total wafer revenue
The newest node had already reached reportable revenue during its initial high-volume ramp.
Showing 5 of 11 sources.
Risks & Indicators
Erosion risks
- Semiconductor downcycles can turn fixed-cost scale into negative operating leverage.
- Government subsidies can help Samsung, Intel, Rapidus and regional foundries build uneconomic capacity.
- Geopolitical risk around Taiwan could impair customer willingness to concentrate supply.
- A major process inflection could reset accumulated yield advantages.
- Samsung or Intel Foundry could close the gap at a future node.
- Trade-secret leakage or talent loss could weaken process know-how advantages.
Leading indicators
- Advanced-node wafer capacity additions
- Capacity utilization by node
- Capex intensity versus Samsung and Intel Foundry
- Equipment lead times and fab ramp schedules
- 2nm and 16-angstrom ramp milestones
- Advanced-node revenue share
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