VOL. XCIV, NO. 247
★ WIDE MOAT STOCKS & COMPETITIVE ADVANTAGES ★
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Taiwan Semiconductor Manufacturing Company Limited
2330 · Taiwan Stock Exchange
Weighted average of segment moat scores, combining moat strength, durability, confidence, market structure, pricing power, and market share.
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Overview
TSMC is a dedicated semiconductor foundry and advanced backend services provider, with net revenue driven primarily by wafer fabrication and supplemented by packaging/testing, mask making, and design/royalty income. Its strongest moat is at the leading edge (7nm and below), where scale/capex intensity and process know-how combine with a broad design ecosystem (OIP) to reduce customer design risk and reinforce stickiness. In mature and specialty nodes, breadth across many technologies and strong operations support utilization and reliability, though competition is tougher and pricing power is lower. TSMC's advanced packaging (3DFabric/CoWoS) is strategically important for AI/HPC systems by enabling high-bandwidth integration of logic chiplets with HBM. Key risks include geopolitical concentration in Taiwan, subsidized competitive catch-up, and semiconductor cycle volatility.
Primary segment
Leading-edge Foundry (7nm and below)
Market structure
Quasi-Monopoly
Market share
70%-72% (reported)
HHI: 5,165
Coverage
3 segments · 7 tags
Updated 2025-12-28
Segments
Leading-edge Foundry (7nm and below)
Leading-edge semiconductor foundry services (<=7nm logic process technologies)
Revenue
74%
Structure
Quasi-Monopoly
Pricing
strong
Share
70%-72% (reported)
Peers
Mature & Specialty Foundry (16nm and above + specialty processes)
Mature-node and specialty semiconductor foundry services (>=16nm and specialty processes)
Revenue
26%
Structure
Oligopoly
Pricing
moderate
Share
—
Peers
Advanced Packaging & 3DFabric (CoWoS, InFO, SoIC)
Advanced packaging and 3D integration services for HPC/AI and chiplet systems
Revenue
—
Structure
Oligopoly
Pricing
strong
Share
—
Peers
Moat Claims
Leading-edge Foundry (7nm and below)
Leading-edge semiconductor foundry services (<=7nm logic process technologies)
Revenue_share is proxied from 3Q25 wafer revenue mix: advanced technologies (7nm and below) were 74% of total wafer revenue (TSMC 3Q25 Management Report). This is not identical to total net revenue.
Capex Knowhow Scale
Supply
Capex Knowhow Scale
Strength
Durability
Confidence
Evidence
TSMC explicitly frames its scale/capacity in advanced technologies as a competitive advantage; sustained multi-tens-of-billions annual capex and process know-how raise barriers at the leading edge.
Erosion risks
- Heavy subsidized capacity build by rivals (Samsung/Intel) narrows the gap
- Major process execution miss (yield/reliability) damages customer trust
- Geopolitical escalation or disruption in Taiwan constrains supply
Leading indicators
- Leading-edge market share and ASP trend
- 2nm ramp milestones and defect density/yield commentary
- Rival node roadmap progress (Samsung/Intel) and customer wins
Counterarguments
- Samsung Foundry and Intel Foundry may close the node gap with aggressive investment
- Large customers can dual-source to reduce concentration risk even if it costs more
Ecosystem Complements
Network
Ecosystem Complements
Strength
Durability
Confidence
Evidence
TSMC's Open Innovation Platform (OIP) ties process technology to a broad EDA/IP/DFM/backend-services ecosystem, reducing design risk and reinforcing stickiness for leading-edge tape-outs.
Erosion risks
- Multi-foundry design flows and portable IP reduce dependence on any one foundry
- Rivals replicate ecosystem programs and improve tool/IP availability
Leading indicators
- Breadth/depth of certified EDA tools and silicon-proven IP portfolio
- Design-start share at leading nodes (<=5nm) across key customers
Counterarguments
- EDA/IP ecosystems are not exclusive; large customers can use similar tools across foundries
- Some leading customers have internal design enablement and can port with enough time/cost
Design In Qualification
Demand
Design In Qualification
Strength
Durability
Confidence
Evidence
Leading-edge chips require process-specific design rules, IP, and qualification; porting to another foundry/node adds cost, delay, and yield risk-especially for HPC/AI parts.
Erosion risks
- Chiplet modularity and standard interfaces reduce redesign/porting costs
- Major customers fund second-source enablement as a strategic risk hedge
Leading indicators
- Evidence of multi-sourcing for the same leading-edge product generation
- Adoption of standardized chiplet interconnect ecosystems
Counterarguments
- The largest customers can absorb porting cost to diversify geopolitical risk
- Design portability improves over time as EDA/IP ecosystems mature
Benchmark Pricing Power
Financial
Benchmark Pricing Power
Strength
Durability
Confidence
Evidence
TSMC describes setting pricing levels for defined periods with customers; when leading-edge capacity is scarce and differentiation is high, this supports strong negotiated pricing (though cycles still matter).
Erosion risks
- Down-cycle demand weakens utilization and pricing leverage
- Rivals add comparable capacity and compete aggressively on price
Leading indicators
- Utilization rates and ASP commentary by node
- Gross margin trend through the cycle
Counterarguments
- Pricing is negotiated; hyperscale/mega-customers can pressure terms
- Regulatory/geopolitical constraints could limit customer demand or mix
Mature & Specialty Foundry (16nm and above + specialty processes)
Mature-node and specialty semiconductor foundry services (>=16nm and specialty processes)
Revenue_share is proxied from 3Q25 wafer revenue mix: non-advanced technologies (above 7nm) were ~26% of total wafer revenue (TSMC 3Q25 Management Report).
Scope Economies
Supply
Scope Economies
Strength
Durability
Confidence
Evidence
Breadth across many process nodes plus adjacent services (packaging/testing/masks/design) supports sticky customer relationships and higher fab loading across cycles.
Erosion risks
- Mature nodes face greater commoditization and price competition
- China capacity additions pressure utilization and pricing in mature processes
Leading indicators
- Utilization rate and price trend in 28nm+ nodes
- Customer concentration and end-market restocking cycles
Counterarguments
- Many mature nodes are competitively supplied by UMC/SMIC/GF with similar capabilities
- Customers may dual-source mature-node parts to optimize cost and resilience
Operational Excellence
Supply
Operational Excellence
Strength
Durability
Confidence
Evidence
Operational execution (cost improvement and utilization management) supports margins and reliability-important in automotive/industrial and long-life products.
Erosion risks
- Rapid capacity build by competitors drives underutilization and margin pressure
- Energy and labor cost inflation reduces cost advantage
Leading indicators
- Gross margin and operating margin through cycles
- On-time delivery and quality metrics (customer returns/escapes)
Counterarguments
- Operational advantages can be competed away as others adopt similar best practices
- Mature-node economics are more sensitive to utilization than process leadership
Benchmark Pricing Power
Financial
Benchmark Pricing Power
Strength
Durability
Confidence
Evidence
TSMC's ability to set pricing levels applies across nodes, but mature-node pricing is more exposed to competition and cyclical utilization swings.
Erosion risks
- Price competition from foundries focused on mature nodes
- Customer mix shifts toward lower-value commodity processes
Leading indicators
- Mature-node ASP trends and discounting commentary
- Capacity additions and utilization rates in 28nm and above
Counterarguments
- Customers can often re-source mature-node wafers faster than leading-edge nodes
- OSAT/IDM alternatives may constrain pricing
Advanced Packaging & 3DFabric (CoWoS, InFO, SoIC)
Advanced packaging and 3D integration services for HPC/AI and chiplet systems
TSMC discloses packaging/testing as part of its revenue mix, but does not break out advanced packaging revenue separately in the cited sources.
Keystone Component
Supply
Keystone Component
Strength
Durability
Confidence
Evidence
CoWoS-class advanced packaging is positioned by TSMC as best-in-class for AI/HPC systems that integrate logic chiplets with HBM; scarce capacity can become a bottleneck that increases leverage.
Erosion risks
- OSATs and competitors expand advanced packaging capacity and narrow the scarcity premium
- Architectural shifts reduce dependency on CoWoS-style solutions
Leading indicators
- CoWoS/advanced packaging capacity expansion and lead times
- AI accelerator demand vs HBM supply and packaging throughput
Counterarguments
- Large customers may diversify packaging across OSATs and competitors to reduce bottlenecks
- Packaging innovation can diffuse quickly once equipment and recipes are widely available
Capex Knowhow Scale
Supply
Capex Knowhow Scale
Strength
Durability
Confidence
Evidence
Advanced packaging requires specialized capex and deep process integration with leading-edge wafer fabs; TSMC is explicitly allocating capex to expand advanced packaging capacity.
Erosion risks
- Competitors match capex and close the gap in advanced packaging capability
- Demand normalizes after AI-cycle peak, reducing returns on new packaging capacity
Leading indicators
- Capex line items and commentary for advanced packaging expansion
- Advanced packaging revenue/mix disclosure (if provided) and margins
Counterarguments
- Packaging capex is large but not as exclusive as leading-edge lithography; OSATs can invest too
- Customer bargaining power can rise once supply catches up
Design In Qualification
Demand
Design In Qualification
Strength
Durability
Confidence
Evidence
Heterogeneous integration (logic chiplets + HBM) requires package co-design and qualification; switching packaging flows/providers can impose redesign and risk for high-power AI systems.
Erosion risks
- Standardized chiplet/package interfaces reduce switching costs
- More packaging options (interposers, RDL, fan-out) become interoperable
Leading indicators
- Growth of standardized chiplet ecosystems and interoperability
- Customer announcements about alternate packaging suppliers
Counterarguments
- Some packaging can be requalified within a product cycle if customers prioritize supply security
- OSATs may offer comparable integration for certain designs at lower cost
Evidence
We believe that our scale and capacity, particularly for advanced technologies, is a major competitive advantage.
Primary-source statement that scale/capacity (especially at advanced nodes) is a competitive advantage.
Our capital expenditures in 2024 were NT$956,007 million (US$29,755 million).
Illustrates the capital intensity needed to compete at the frontier.
OIP ... lowers design barriers ... and first-time silicon success rates.
Shows a structured complements ecosystem (tools, IP, DFM, backend) that improves customer outcomes and reinforces demand-side moat.
OIP promotes innovation ... using TSMC's IP, DFM capabilities, process technology and backend services.
Process-specific IP/DFM and backend integration increase qualification/porting friction versus switching to a different foundry.
We count among our customers ... including ... Advanced Micro Devices ... NVIDIA ... Qualcomm ...
TSMC names multiple leading customers; supports the 'design-in' thesis and the segment key-customer list.
Showing 5 of 14 sources.
Risks & Indicators
Erosion risks
- Heavy subsidized capacity build by rivals (Samsung/Intel) narrows the gap
- Major process execution miss (yield/reliability) damages customer trust
- Geopolitical escalation or disruption in Taiwan constrains supply
- Multi-foundry design flows and portable IP reduce dependence on any one foundry
- Rivals replicate ecosystem programs and improve tool/IP availability
- Chiplet modularity and standard interfaces reduce redesign/porting costs
Leading indicators
- Leading-edge market share and ASP trend
- 2nm ramp milestones and defect density/yield commentary
- Rival node roadmap progress (Samsung/Intel) and customer wins
- Breadth/depth of certified EDA tools and silicon-proven IP portfolio
- Design-start share at leading nodes (<=5nm) across key customers
- Evidence of multi-sourcing for the same leading-edge product generation
Curation & Accuracy
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